1. Field of Invention
The present invention relates to an Automatic Test Pattern Generator (ATPG) testing circuit and testing method for testing a IC chip, and, more particularly, to ATPG testing circuit and testing method at high testing speed.
2. Description of Related Art
An Automatic Test Pattern Generator (ATPG) is a software design tool that simulates the overall functionality of the design or individual circuits within the design of an integrated circuit and generates test vectors for testing the stuck at “0” or “1” overall circuit node of the design. Through the use of these test vectors, an Automatic Testing Equipment (ATE) sends the test vectors, created by ATPG, to the under test device (UTD) and observes the output of UTD to verify it has may provide a particular degree of fault coverage or fault simulation for the circuitry in the product. Specifically, automatic test pattern generation techniques provide test patterns for stuck-at faults, transition faults and path delay faults. The ATE is used in a manufacturing environment to test the die at wafer-level and in packaged tests. During testing of a die, test signals are provided through input or input/output (I/O) buffers on the die, and the test results are monitored on output or I/O buffers.
Testing of digital systems, such as the core logic of an integrated circuit, is typically performed by loading test patterns into scan chains in the system then capturing the logic values of combination logic between flip flop of scan chain. The captured information are shift out and compared by ATE.
FIG. 1 shows a conventional ATPG testing mechanism for testing a chip 100. As shown in FIG. 1, the chip to be tested 100 at least includes an output buffer 105 and at least one scan chain. The scan chain at least has a plurality of flip-flops 101 and a plurality of combinational logics 102a, 102b . . . . During test, the ATE 120 sends out ATPG test patterns to the chip 100. The ATPG test patterns are sequentially input into the combinational logics 102a, 102b . . . via the flip-flops 101, triggered by the scan clock scan-clk. After the combinational logics 102a, 102b . . . receive the ATPG test patterns, they will output a logic value to the back-stage flip-flop 101. Then, the logic values are sequentially output from the output buffer 105 to the ATE 120 via the load board 110. Then, the ATE 120 compares the received ATPG test patterns with the ATPG test patterns originally sent out to the chip 100. Based on the comparison result, the ATE 120 determines whether the chip 100 is pass or failed.
However, in tradition, the test speed of ATPG is limited by output buffer driving strength and by pin load of ATE. In other words, if driving strength of generic output buffer of IC chips is not enough or the pin load of ATE is heavy, the test speed of the ATE may not be high. Further, when the output buffer sends out the ATPG test patterns to the ATE, the output buffer will suffer from large loading which is caused by the load board 110 and the ATE 120.
For example, if driving strength of the output buffer 105 is 16 mA while the pin load of ATE is 87 p, then the maximum test clock frequency is about 31 MHz for full swing. Further, it takes time to transmit long ATPG patterns for testing.
The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above.